1. Field of the Invention
The present invention relates to a sync pattern detection apparatus and method which detect a sync pattern inserted into a digital signal sequence at a predetermined interval.
2. Description of the Related Art
An ID number and other data are added to a specific unit of digital data to form a data block. An error-detecting code, an error-correcting code, and the like are added to the data block to form a data block with error code. When the data block with error code is to be recorded on a recording medium or transmitted to a transmission path, a sync pattern is inserted into the data block with error code at a predetermined interval at the time of data modulation processing.
In playback processing, a sync pattern is detected from a signal input to a playback processing apparatus. From the position of the sync pattern, the data is divided and demodulated for each symbol. In addition, data block arrangement information is obtained on the basis of order information from the sync pattern. Error-correcting processing and the like are executed to reconstruct a playback signal.
As described above, sync pattern detection is the most important function in the playback system. It is no exaggeration to say that the sync pattern detection capability decides the playback capability.
A sync pattern processing section detects a sync pattern, checks its reliability, and synchronizes the period counter (frame counter) of the sync pattern interval to the detection timing. Accordingly, a signal that controls data symbol division and demodulation of a digital signal stream and data block arrangement of demodulated data is generated. Functions that the sync pattern processing section is required of are as follows. The frame counter must be synchronized to the playback sync pattern. Even when a sync pattern is omitted due to a signal defect, playback control synchronization must be correctly established. The sync pattern processing section must not sense a pseudo sync pattern generated in modulated data. A read clock to be used to read a digital signal or sync pattern is generated from a playback signal stream by using a PLL (Phase Locked Loop) circuit. If a signal stream is destroyed by some error, the period of the PLL varies, resulting in a change in number of clocks between sync patterns. The sync pattern processing section must be configured to execute proper synchronization processing even in such a case.
To meet the requirements for sync detection protection, a synchronous circuit is proposed in Jpn. Pat. Appln. KOKOKU Publication No. 5-74147.
The sync pattern detection protection circuit disclosed in this prior art uses an asynchronous time limit control scheme to execute re-synchronization processing when it goes out of sync. This circuit is disadvantageous in that it has a plurality of combinations of frame counters and detection window generators because of its weak pseudo synchronization eliminating capability in the first re-synchronization, and it executes re-synchronization of the main frame counter only by a sync pattern that is confirmed in advance by the sub frame counter. In this sync pattern detection protection circuit, a synchronous state or an asynchronous state is detected on the basis of the length of the period without synchronization processing. That is, restoring from the asynchronous state to the synchronous state cannot be done in a short time.